`timescale 1ns / 1ns

module img_frame #(
    parameter [15:0] IMAGE_X = 8,
    parameter [15:0] IMAGE_Y = 8,
    parameter [15:0] STEP_X = 8,
    parameter [15:0] STEP_Y = 8
)
(
    input clk,
    input wr,
    input [7:0] x, y,
    input [STEP_X-1:0][STEP_Y-1:0][23:0] data
);

reg [STEP_X-1:0][STEP_Y-1:0][23:0] frame[IMAGE_X-1:0][IMAGE_Y-1:0];

always @(posedge clk) begin
    if (wr) begin
        $display("FrameBuffer %d %d Write", x, y);
        frame[x][y] <= data;
    end
end

endmodule